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ciii51001-2.4 ? 2012 altera corporation. all rights reserved. altera, arria, cyclone, hardcopy, max, megaco re, nios, quartus and stratix word s and logos are trademarks of altera corporat ion and registered in the u.s. patent and trademark office and in other countries. all other w ords and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specifications in accordance wi th altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability ar ising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customer s are advised to obtain the latest version of device specificat ions before relying on any published information and before placing orders for products or services. cyclone iii device handbook volume 1 july 2012 subscribe iso 9001:2008 registered 1. cyclone iii device family overview cyclone ? iii device family offers a unique combination of high functionality, low power and low cost. based on taiwan semiconductor manufacturing company (tsmc) low-power (lp) process technology, silicon optimizations and software features to minimize power consumption, cy clone iii device family provides the ideal solution for your high-volume, low-power, and cost-sensitive applications. to address the unique design needs, cyclone iii device family offers the following two variants: cyclone iii?lowest power, high functionality with the lowest cost cyclone iii ls?lowest power fpgas with security with densities ranging from about 5,00 0 to 200,000 logic elements (les) and 0.5 megabits (mb) to 8 mb of memory fo r less than ? watt of static power consumption, cyclone iii device family makes it easier for you to meet your power budget. cyclone iii ls devices are the first to implement a suite of security features at the silicon, software, and intellectual property (ip) level on a low-power and high-functionality fpga platform. this suite of security features protects the ip from tampering, reverse engineer ing and cloning. in addition, cyclone iii ls devices support design separation which enables you to introduce redundancy in a single chip to reduce size, weight, and power of your application. this chapter contains the following sections: ?cyclone iii device family features? on page 1?1 ?cyclone iii device family architecture? on page 1?6 ?reference and ordering information? on page 1?12 cyclone iii device family features cyclone iii device family of fers the following features: lowest power fpgas lowest power consumption with tsmc low-power process technology and altera ? power-aware design flow low-power operation offers the following benefits: extended battery life for portab le and handheld applications reduced or eliminated cooling system costs operation in thermally-challenged environments hot-socketing operation support july 2012 ciii51001-2.4
1?2 chapter 1: cyclone iii device family overview cyclone iii device family features cyclone iii device handbook july 2012 altera corporation volume 1 design security feature cyclone iii ls devices offer the fo llowing design security features: configuration security using advanced en cryption standard (aes) with 256-bit volatile key routing architecture optimized for desi gn separation flow with the quartus ? ii software design separation flow achieves both physical and functional isolation between design partitions ability to disable external jtag port error detection (ed) cy cle indicator to core provides a pass or fail indicator at every ed cycle provides visibility over intentional or unintentional change of configuration random access memory (cram) bits ability to perform zeroization to clear contents of the fpga logic, cram, embedded memory, and aes key internal oscillator enables system monitor and health check capabilities increased system integration high memory-to-logic and multiplier-to-logic ratio high i/o count, low-and mid-range density devices for user i/o constrained applications adjustable i/o slew rates to improve signal integrity supports i/o standards such as lvttl , lvcmos, sstl, hstl, pci, pci-x, lvpecl, bus lvds (blvds), lvds, mini-lvds, rsds, and ppds supports the multi-value on-chip termin ation (oct) calibration feature to eliminate variations over process, voltage, and temperature (pvt) four phase-locked loops (plls) per devi ce provide robust clock management and synthesis for device clock management, external system clock management, and i/o interfaces five outputs per pll cascadable to save i/os, ease pcb routing, and reduce jitter dynamically reconfigurable to change ph ase shift, frequency multiplication or division, or both, and input frequency in the system without reconfiguring the device remote system upgrade without th e aid of an external controller dedicated cyclical redundancy code checke r circuitry to detect single-event upset (seu) issues nios ? ii embedded processor for cyclone iii device family, offering low cost and custom-fit embedded pr ocessing solutions
chapter 1: cyclone iii device family overview 1?3 cyclone iii device family features july 2012 altera corporation cyclone iii device handbook volume 1 wide collection of pre-built and verifi ed ip cores from altera and altera megafunction partners program (ampp) partners supports high-speed external memory interfaces such as ddr, ddr2, sdr sdram, and qdrii sram auto-calibrating phy feature eases the timing closure process and eliminates variations with pvt for ddr, ddr2, and qdrii sram interfaces cyclone iii device family supports vertical migration that allows you to migrate your device to other devices with the same de dicated pins, configur ation pins, and power pins for a given package-across device densit ies. this allows you to optimize device density and cost as your design evolves. table 1?1 lists cyclone iii devi ce family features. table 1?1. cyclone iii device family features family device logic elements number of m9k blocks total ram bits 18 x 18 multipliers plls global clock networks maximum user i/os cyclone iii ep3c5 5,136 46 423,936 23 2 10 182 ep3c10 10,320 46 423,936 23 2 10 182 ep3c16 15,408 56 516,096 56 4 20 346 ep3c25 24,624 66 608,256 66 4 20 215 ep3c40 39,600 126 1,161,216 126 4 20 535 EP3C55 55,856 260 2,396,160 156 4 20 377 ep3c80 81,264 305 2,810,880 244 4 20 429 ep3c120 119,088 432 3,981,312 288 4 20 531 cyclone iii ls ep3cls70 70,208 333 3,068,928 200 4 20 429 ep3cls100 100,448 483 4,451,328 276 4 20 429 ep3cls150 150,848 666 6,137,856 320 4 20 429 ep3cls200 198,464 891 8,211,456 396 4 20 429
1?4 chapter 1: cyclone iii device family overview cyclone iii device family features cyclone iii device handbook july 2012 altera corporation volume 1 table 1?2 lists cyclone iii device family package options, i/o pins, and differential channel counts. table 1?2. cyclone iii device family package options, i/o pin and differential channel counts (1) , (2) , (3) , (4) , (5) family package e144 (7) m164 p240 f256 u256 f324 f484 u484 f780 cyclone iii (8) ep3c5 94, 22 106, 28 ? 182, 68 182, 68 ? ? ? ? ep3c10 94, 22 106, 28 ? 182, 68 182, 68 ? ? ? ? ep3c16 84, 19 92, 23 160, 47 168, 55 168, 55 ? 346, 140 346, 140 ? ep3c25 82, 18 ? 148, 43 156, 54 156, 54 215, 83 ? ? ? ep3c40 ? ? 128, 26 ? ? 195, 61 331, 127 331, 127 535, 227 (6) EP3C55 ? ? ? ? ? ? 327, 135 327, 135 377, 163 ep3c80 ? ? ? ? ? ? 295, 113 295, 113 429, 181 ep3c120 ? ? ? ? ? ? 283, 106 ? 531, 233 cyclone iii ls ep3cls70 ? ? ? ? ? ? 294, 113 294, 113 429, 181 ep3cls100 ? ? ? ? ? ? 294, 113 294, 113 429, 181 ep3cls150 ? ? ? ? ? ? 226, 87 ? 429, 181 ep3cls200 ? ? ? ? ? ? 226, 87 ? 429, 181 notes to table 1?2 : (1) for each device package, the fi rst number indicates the number of the i/o pi n; the second number in dicates the differential channel count. (2) for more information about device packag ing specifications, refe r to the cyclone iii package and thermal resistance webpage. (3) the i/o pin numbers are the maximum i/o counts (including clock input pins) suppor ted by the device pack age combination and can be affected by the configuration schem e selected for the device. (4) all packages are available in lead-free and leaded options. (5) vertical migration is no t supported between cyclone iii and cyclone iii ls devices. (6) the ep3c40 device in the f780 package su pports restricted vertical mi gration. maximum user i/os are restricted to 510 i/os i f you enable migration to the ep3c120 and are using volt age referenced i/o standards. if you are not using voltage referenced i/o standards, you can increase the maximum number of i/os. (7) the e144 package has an exposed pad at the bottom of the package. this exposed pad is a ground pad that must be connected to the ground plane on your pcb. use this exposed pad for el ectrical connectivity and not for thermal purposes. (8) all cyclone iii device ubga packages are supported by the qu artus ii software version 7.1 sp1 and later, with the exception of the ubga packages of ep3c16, which are supported by the quartus ii software version 7.2.
chapter 1: cyclone iii device family overview 1?5 cyclone iii device family features july 2012 altera corporation cyclone iii device handbook volume 1 table 1?3 lists cyclone iii device family package sizes. table 1?4 lists cyclone iii device family speed grades. table 1?3. cyclone iii device family package sizes family package pitch (mm) nominal area (mm 2 ) length x width (mm ? mm) height (mm) cyclone iii e144 0.5 484 22 ? 22 1.60 m164 0.5 64 8 ? 8 1.40 p240 0.5 1197 34.6 ? 34.6 4.10 f256 1.0 289 17 ? 17 1.55 u256 0.8 196 14 ? 14 2.20 f324 1.0 361 19 ? 19 2.20 f484 1.0 529 23 ?? 23 2.60 u484 0.8 361 19 ? 19 2.20 f780 1.0 841 29 ? 29 2.60 cyclone iii ls f484 1.0 529 23 ? 23 2.60 u484 0.8 361 19 ? 19 2.20 f780 1.0 841 29 ? 29 2.60 table 1?4. cyclone iii device family speed grades (part 1 of 2) family device e144 m164 p240 f256 u256 f324 f484 u484 f780 cyclone iii ep3c5 c7, c8, i7, a7 c7, c8, i7 ? c6, c7, c8, i7, a7 c6, c7, c8, i7, a7 ???? ep3c10 c7, c8, i7, a7 c7, c8, i7 ? c6, c7, c8, i7, a7 c6, c7, c8, i7, a7 ???? ep3c16 c7, c8, i7, a7 c7, c8, i7 c8 c6, c7, c8, i7, a7 c6, c7, c8, i7, a7 ? c6, c7, c8, i7, a7 c6, c7, c8, i7, a7 ? ep3c25 c7, c8, i7, a7 ?c8 c6, c7, c8, i7, a7 c6, c7, c8, i7, a7 c6, c7, c8, i7, a7 ??? ep3c40 ? ? c8 ? ? c6, c7, c8, i7, a7 c6, c7, c8, i7, a7 c6, c7, c8, i7, a7 c6, c7, c8, i7 EP3C55 ? ? ? ? ? ? c6, c7, c8, i7 c6, c7, c8, i7 c6, c7, c8, i7 ep3c80 ? ? ? ? ? ? c6, c7, c8, i7 c6, c7, c8, i7 c6, c7, c8, i7 ep3c120 ? ? ? ? ? ? c7, c8, i7 ? c7, c8, i7
1?6 chapter 1: cyclone iii device family overview cyclone iii device family architecture cyclone iii device handbook july 2012 altera corporation volume 1 table 1?5 lists cyclone iii device fa mily configuration schemes. cyclone iii device family architecture cyclone iii device family includ es a customer-defined feature set that is optimized for portable applications and offers a wide range of density, memory, embedded multiplier, and i/o options. cyclone iii de vice family supports numerous external memory interfaces and i/o protocols that are common in high-volume applications. the quartus ii software features and paramete rizable ip cores make it easier for you to use the cyclone iii device family interfaces and protocols. the following sections provide an overview of the cyclone iii devi ce family features. logic elements and logic array blocks the logic array block (lab) consists of 16 logic elements and a lab-wide control block. an le is the smallest unit of logic in the cyclone iii device family architecture. each le has four inputs, a four-input look-up table (lut), a register, and output logic. the four-input lut is a function generator that can implement any function with four variables. f for more information about les and labs, refer to the logic elements and logic array blocks in the cyclone iii device family chapter. cyclone iii ls ep3cls70 ? ? ? ? ? ? c7, c8, i7 c7, c8, i7 c7, c8, i7 ep3cls100 ? ? ? ? ? ? c7, c8, i7 c7, c8, i7 c7, c8, i7 ep3cls150 ? ? ? ? ? ? c7, c8, i7 ? c7, c8, i7 ep3cls200 ? ? ? ? ? ? c7, c8, i7 ? c7, c8, i7 table 1?4. cyclone iii device family speed grades (part 2 of 2) family device e144 m164 p240 f256 u256 f324 f484 u484 f780 table 1?5. cyclone iii device family configuration schemes configuration scheme cyclone iii cyclone iii ls active serial (as) v v active parallel (ap) v ? passive serial (ps) v v fast passive parallel (fpp) v v joint test action group (jtag) v v
chapter 1: cyclone iii device family overview 1?7 cyclone iii device family architecture july 2012 altera corporation cyclone iii device handbook volume 1 memory blocks each m9k memory block of the cyclone iii device family provides nine kbits of on-chip memory capable of operating at up to 315 mhz for cyclone iii devices and up to 274 mhz for cyclone iii ls devices. the embedded memory structure consists of m9k memory blocks columns that you can conf igure as ram, first- in first-out (fifo) buffers, or rom. the cyclone iii device family memory blocks are optimized for applications such as high throughout packet processing, embedded processor program, and embedded data storage. the quartus ii software allows you to take advantage of the m9k memory blocks by instantiating memory using a dedicated mega function wizard or by inferring memory directly from the vhdl or verilog source code. m9k memory blocks support single-port, simple dual-port, and true dual-port operation modes. single-port mode and simple dual-port mode are supported for all port widths with a configuration of 1, 2, 4, 8, 9, 16, 18, 32, and 36. true dual-port is supported in port widths with a configuration of 1, 2, 4, 8, 9, 16, and 18. f for more information about memory blocks, refer to the memory blocks in the cyclone iii device family chapter. embedded multipliers and digi tal signal processing support cyclone iii devices support up to 288 embedd ed multiplier blocks and cyclone iii ls devices support up to 396 embedded mult iplier blocks. each block supports one individual 18 18-bit multiplier or two individual 9 9-bit multipliers. the quartus ii software includes megafunction s that are used to control the operation mode of the embedded multiplier blocks based on user parameter settings. multipliers can also be inferred directly from the vhdl or verilog source code. in addition to embedded multipliers, cyclone iii device family includes a combination of on-chip resources and external interf aces, making them ideal for increasing performance, reducing system cost, and lo wering the power consumption of digital signal processing (dsp) systems. you can use cyclone iii device family alone or as dsp device co-processors to improve price-to-performance ratios of dsp systems. the cyclone iii device family dsp system design support includes the following features: dsp ip cores: common dsp processing functions such as finite impulse response (fir), fast fourier transform (fft), and numerically controlled oscillator (nco) functions suites of common video and image processing functions complete reference designs for end-market applications dsp builder interface tool between the quartus ii software and the mathworks simulink and matlab design environments dsp development kits f for more information about embedded multipliers and digital signal processing support, refer to the embedded multipliers in cyclone iii devices chapter.
1?8 chapter 1: cyclone iii device family overview cyclone iii device family architecture cyclone iii device handbook july 2012 altera corporation volume 1 clock networks and plls cyclone iii device family includes 20 global clock networks. you can drive global clock signals from dedicated clock pins, du al-purpose clock pins, user logic, and plls. cyclone iii device family includes up to four plls with five outputs per pll to provide robust clock manageme nt and synthesis. you can use plls for device clock management, external system cloc k management, and i/o interfaces. you can dynamically reconfigure the cyclon e iii device family plls to enable auto-calibration of external memory interfaces while the device is in operation. this feature enables the support of multiple in put source frequencies and corresponding multiplication, division, and phase shift requirements. plls in cyclone iii device family may be cascaded to generate up to ten internal clocks and two external clocks on output pins from a sin gle external clock source. f for more pll specifications and information, refer to the cyclone iii device data sheet , cyclone iii ls device data sheet , and clock networks and plls in the cyclone iii device family chapters. i/o features cyclone iii device family has eight i/o ba nks. all i/o banks support single-ended and differential i/o standards listed in table 1?6 . the cyclone iii device family i/o also supports programmable bus hold, programmable pull-up resistors, programma ble delay, programmable drive strength, programmable slew-rate control to optimize signal integrity, and hot socketing. cyclone iii device family supports cali brated on-chip series termination (r s oct) or driver impedance matching (rs) for sing le-ended i/o standards, with one oct calibration block per side. f for more information, refer to the i/o features in the cyclone iii device family chapter. high-speed differential interfaces cyclone iii device family suppo rts high-speed differential interfaces such as blvds, lvds, mini-lvds, rsds, and ppds. these hi gh-speed i/o standards in cyclone iii device family provide high data throughput using a relatively small number of i/o pins and are ideal for low-cost applications . dedicated differential output drivers on the left and right i/o banks can send data rates at up to 875 mbps for cyclone iii devices and up to 740 mbps for cyclone iii ls devices, without the need for external resistors. this saves board space or simplifies pcb routing. top and bottom i/o banks support differential transmission (with the addition of an external resistor network) data rates at up to 640 mbps for both cyclone iii and cyclone iii ls devices. table 1?6. cyclone iii device family i/o standards support type i/o standard single-ended i/o lvttl, lvcmos, sstl, hstl, pci, and pci-x differential i/o sstl, hstl, lvpecl, bl vds, lvds, mini-lvds, rsds, and ppds
chapter 1: cyclone iii device family overview 1?9 cyclone iii device family architecture july 2012 altera corporation cyclone iii device handbook volume 1 f for more information, refer to the high-speed differential in terfaces in the cyclone iii device family chapter. auto-calibrating external memory interfaces cyclone iii device family supports common memory types such as ddr, ddr2, sdr sdram, and qdrii sram. ddr2 sdram memory interfaces support data rates up to 400 mbps for cyclone iii device s and 333 mbps for cyclone iii ls devices. memory interfaces are supported on all si des of cyclone iii device family. cyclone iii device family has the oct, ddr output re gisters, and 8-to-36-bit programmable dq group widths features to enable rapid and robust implementa tion of different memory standards. an auto-calibrating megafunction is availa ble in the quartus ii software for ddr and qdr memory interface phys. this megafuncti on is optimized to take advantage of the cyclone iii device family i/o structure, simplify timing closure requirements, and take advantage of the cyclone iii device family pll dynamic reconfiguration feature to calibrate pvt changes. f for more information, refer to the external memory interfaces in the cyclone iii device family chapter. support for industry-sta ndard embedded processors to quickly and easily create system-level designs using cyclone iii device family, you can select among the 32-bit so ft processor cores: freescale ? v1 coldfire, arm ? cortex m1, or altera nios ? ii, along with a library of 50 other ip blocks when using the system-on-a-programmable-ch ip (sopc) builder tool. sopc builder is an altera quartus ii design tool that facilitates syst em-integration of ip blocks in an fpga design. the sopc builder automatically generates interconnect logic and creates a testbench to verify functionality, saving valuable design time. cyclone iii device family expands the periph eral set, memory, i/o, or performance of legacy embedded processors. single or multiple nios ii embedded processors are designed into cyclone iii device family to provide additional co-processing power, or even replace legacy embedded processors in your system. using the cyclone iii device family and nios ii together provide low-cost, high-performance embedded processing solutions, which in turn allow you to extend the life cycle of your product and improve time-to-market over standard product solutions. 1 separate licensing of the freescale and arm embedded processors are required. hot socketing and power-on-reset cyclone iii device family fe atures hot socketing (also kn own as hot plug-in or hot swap) and power sequencing support without the use of external devices. you can insert or remove a board populated with one or more cyclone iii device family during a system operation without causing undesirable effects to the running system bus or the board that was inserted into the system.
1?10 chapter 1: cyclone iii device family overview cyclone iii device family architecture cyclone iii device handbook july 2012 altera corporation volume 1 the hot socketing feature allows you to use fpgas on pcbs that also contain a mixture of 3.3-v, 2.5-v, 1.8-v, 1.5-v, and 1.2-v devices. the cyclone iii device family hot socketing feature eliminates power-up sequence requirements for other devices on the board for proper fpga operation. f for more information about hot socketing and power-on-reset, refer to the hot-socketing and power-on reset in the cyclone iii device family chapter. seu mitigation cyclone iii ls devices offer built-in error dete ction circuitry to detect data corruption due to soft errors in the cram cells. this feature allows cram contents to be read and verified to match a configuration-comp uted crc value. the quartus ii software activates the built-in 32-bit crc checker, wh ich is part of the cyclone iii ls device. f for more information about seu mitigation, refer to the seu mitigation in the cyclone iii device family chapter. jtag boundary scan testing cyclone iii device family su pports the jtag ieee std. 1149.1 specification. the boundary-scan test (bst) architecture offers the capability to test pin connections without using physical test probes and capt ures functional data while a device is operating normally. boundary-scan cells in the cyclone iii device family can force signals onto pins or capture data from pins or from logic array signals. forced test data is serially shifted into the boundary-scan cells. captur ed data is serially shifted out and externally compared to expected resu lts. in addition to bst, you can use the ieee std. 1149.1 controller for the cyclon e iii ls device in-circuit reconfiguration (icr). f for more information about jtag boundary scan testing, refer to the ieee 1149.1 (jtag) boundary-scan testing fo r the cyclone iii device family chapter. quartus ii software support the quartus ii software is the leading design software for performance and productivity. it is the only complete design solution for cplds, fpgas, and asics in the industry. the quartus ii software includes an integrated development environment to accelerate system-level desi gn and seamless integration with leading third-party software tools and flows. the cyclone iii ls devices provide both phys ical and functional separation between security critical design partitions. cycl one iii ls devices offer isolation between design partitions. this ensures that device errors do not propagate from one partition to another, whether unintentional or intentional. the quartus ii software design separation flow facilitates the creation of separation regions in cyclone iii ls devices by tightly controlling the routing in and between the logiclock regions. for ease of use, the separation flow integrates in the existing incremental compilation flow. f for more information about the quartus ii software features, refer to the quartus ii handbook .
chapter 1: cyclone iii device family overview 1?11 cyclone iii device family architecture july 2012 altera corporation cyclone iii device handbook volume 1 configuration cyclone iii device family us es sram cells to store conf iguration data. configuration data is downloaded to cyclone iii device family each time the device powers up. low-cost configuration options include the al tera epcs family seri al flash devices as well as commodity parallel flash configuration options. these options provide the flexibility for general-purpose applicatio ns and the ability to meet specific configuration and wake-up time requirements of the applications. cyclone iii device family supports the as, ps, fpp, and jtag configuration schemes. the ap configuration scheme is only su pported in cyclone iii devices. f for more information about configuration, refer to the configuration, design security, and remote system upgrades in the cyclone iii device family chapter. remote system upgrades cyclone iii device family offers remote system upgrade without an external controller. the remote system upgrade capabi lity in cyclone iii device family allows system upgrades from a remote location. soft logic (either the nios ii embedded processor or user logic) implemented in cyclone iii device family can download a new configuration image from a remote location, store it in configuration memory, and direct the dedicated remote system up grade circuitry to start a reconfiguration cycle. the dedicated circui try performs error detection during and after the configuration process, and can recover from an error condition by reverting to a safe configuration image. the dedicated circuitry also provides error status information. cyclone iii devices support re mote system upgrade in the as and ap configuration scheme. cyclone iii ls devices support remote system upgrade in the as configuration scheme only. f for more information, refer to the configuration, design secu rity, and remote system upgrades in the cyclone iii device family chapter. design security (cyclone iii ls devices only) cyclone iii ls devices offer design security fe atures which play a vital role in the large and critical designs in the competitive military and commercial environments. equipped with the configuration bit stream encryption and anti-tamper features, cyclone iii ls devices protect your design s from copying, reverse engineering and tampering. the configuration security of cy clone iii ls devices uses aes with 256-bit security key. f for more information, refer to the configuration, design secu rity, and remote system upgrades in cyclone iii device family chapter.
1?12 chapter 1: cyclone iii device family overview reference and ordering information cyclone iii device handbook july 2012 altera corporation volume 1 reference and ordering information figure 1?1 and figure 1?2 show the ordering codes for cyclone iii and cyclone iii ls devices. figure 1?1. cyclone iii device packaging ordering information family signature package type package code operating temperature speed grade optional suffix indicates specific device options or shipment method ep3c : cyclone iii 5 : 5,136 logic elements 10 : 10,320 logic elements 16 : 15,408 logic elements 25 : 24,624 logic elements 25e : 24,624 logic elements 40 : 39,600 logic elements 55 : 55,856 logic elements 80 : 81,264 logic elements 120 : 119,088 logic elements e : plastic enhanced quad flat pack (eqfp) q : plastic quad flat pack (pqfp) f : fineline ball-grid array (fbga) u : ultra fineline ball-grid array (ubga) m : micro fineline ball-grid array (mbga) 144 : 144 pins 164 : 164 pins 240 : 240 pins 256 : 256 pins 324 : 324 pins 484 : 484 pins 780 : 780 pins c : commercial temperature (t j = 0 c to 85 c) i : industrial temperature (t j = -40 c to 100 c) a : automotive temperature (t j = -40 c to 125 c) 6 (fastest) 7 8 n : lead-free packaging es : engineering sample ep3c 25 f 324 c 7 n member code figure 1?2. cyclone iii ls device packaging ordering information family signature package type package code operating temperature speed grade optional suffix indicates specific device options or shipment method ep3cls : cyclone iii ls 70 : 70,208 logic elements 100 : 100,448 logic elements 150 : 150,848 logic elements 200 : 198,464 logic elements f : fineline ball-grid array (fbga) u : ultra fineline ball-grid array (ubga) 484 : 484 pins 780 : 780 pins c : commercial temperature (t j = 0 c to 85 c) i : industrial temperature (t j = -40 c to 100 c) 7 (fastest) 8 n : lead-free packaging es : engineering sample ep3cls 70 f 484 c 7 n member code
chapter 1: cyclone iii device family overview 1?13 document revision history july 2012 altera corporation cyclone iii device handbook volume 1 document revision history table 1?7 lists the revision history for this document. table 1?7. document revision history date version changes july 2012 2.4 updated 484 pin package code in figure 1?1 . december 2011 2.3 updated table 1?1 and table 1?2. updated figure 1?1 and figure 1?2. updated hyperlinks. minor text edits. december 2009 2.2 minor text edits. july 2009 2.1 minor edit to the hyperlinks. june 2009 2.0 added table 1?5. updated table 1?1, table 1?2, table 1?3, and table 1?4. updated ?introduction?, ?cyclone iii device family architecture?, ?embedded multipliers and digital signal processing support ?, ?clo ck networks and plls ?, ?i/o features ?, ?high-speed differential interfaces ?, ?auto- calibrating external memory interfaces ?, ?quartus ii software support?, ?configuration ?, and ?design security (cyclone iii ls devices only)?. removed ?referenced document? section. october 2008 1.3 updated ?increased system integration? section. updated ?memory blocks? section. updated chapter to new template. may 2008 1.2 added 164-pin micro fineline ball-grid array (mbga) details to table 1?2, table 1?3 and table 1?4. updated figure 1?2 with automotive temperature information. updated ?increased system integration? section, table 1?6, and ?high-speed differential interfaces? section with blvds information. july 2007 1.1 removed the text ?spansion? in ?increased system. integration? and ?configuration? sections. removed trademark symbol from ?multitrack? in ?multitrack interconnect?. removed registered trademark symbol from ?simulink? and ?matlab? from ?embedded multipliers and digital. signal processing support? section. added chapter toc and ?referenced documents? section. march 2007 1.0 initial release.
1?14 chapter 1: cyclone iii device family overview document revision history cyclone iii device handbook july 2012 altera corporation volume 1

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